Md Kamrul Islam
Turning complex IP into verified silicon.
I'm also a HARDWARE RELIABILITY ENTHUSIAST.
Design Verification Engineer with more than 4 years of hands-on experience verifying complex IP across RTL and gate-level domains. Delivered DDR PHY, USB PD Controller, and RTC IP verification — identifying 70+ silicon-critical bugs and achieving >95% coverage closure.
Engineer, researcher, and silicon problem hunter.
Hello! I'm Md Kamrul Islam, a Senior Design Verification Engineer at ULKASEMI Pvt. Limited based in Dhaka, Bangladesh. I work where RTL intent meets real sign-off pressure: UVM testbenches, gate-level simulation, coverage closure, waveform debug, and automation. Humanity invented invisible bugs inside chips and then hired people like me to hunt them. Naturally.
My work combines verification planning, reusable UVM methodology, GLS debug, client communication, and mentoring junior engineers. I'm especially interested in VLSI reliability, ASIC design and verification, secure SoC architecture, and automation that saves engineers from doing the same painful task twice.
Design Verification
Academic Background
Research & Publications
Research interests at the intersection of hardware reliability, intelligent systems, and secure SoC architecture.
Projects with measurable outcomes.
Gate-level sign-off readiness of DDR PHY IP through multi-corner GLS regressions, X-propagation debug, UVM updates, and power-analysis support.
- Resolved 40+ tape-out critical functional issues
- Reduced GLS debug cycles by ~30% via automation
- Led a team of 3 engineers to hit milestones
Refactored RTL-provided linear testbench, automated GLS execution, and debugged X-propagation failures to stabilise regressions.
- Improved GLS readiness and regression stability
- Enabled repeatable GLS execution with lower manual effort
End-to-end verification sign-off of RTC IP with reusable UVMF-style UVM environment, RAL model, coverage model, assertions, and waiver tracking.
- Achieved ~98% functional and code coverage
- Caught 25+ functional bugs
- Reduced verification time by ~30% using Bash automation
Verified USB-PD controller subsystems across RTL and GLS through constrained-random tests, global assertions, coverage models, and regression triage.
- Found 30+ pre-silicon functional bugs
- Contributed to first-silicon success
Built multi-agent UVM testbench for Wishbone-I2C and APB-SPI, and single-agent for APB/AHB; authored test/coverage plans and automation scripts.
- Achieved >90% functional coverage
- Cut test cycle time ~30% with Bash/Python automation
Built a rooftop PV/weather data acquisition setup and ANN/MLP workflow to analyse clean vs. dusty PV module behaviour under real environmental conditions.
- Published 3 IEEE conference papers
- Found temperature as most correlated parameter with PV output
Professional Journey
Technical Expertise
Training & Certifications
Get in Touch
Open to collaborations, opportunities, and conversations about chip design verification, UVM methodology, GLS, and semiconductor engineering.
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