Senior Design Verification Engineer

Md Kamrul Islam

Turning complex IP into verified silicon.

I'm also a HARDWARE RELIABILITY ENTHUSIAST.

Senior Design Verification Engineer with almost 4 years of hands-on experience verifying complex IP across RTL and gate-level domains. Delivered DDR PHY, USB PD Controller, and RTC IP verification — identifying 30+ silicon-critical bugs and achieving >95% coverage closure.

Explore Work Get in Touch
Md Kamrul Islam
Tape-out ready
Debug cycles ↓ 30–40%
●  SENIOR ENGINEER — JAN 2025 → PRESENT
$
0
Silicon-critical
bugs found
>95%
Functional
coverage
0
Client
projects
0
Engineers
mentored
0
Trainees
trained
0
Faster
debug cycles
// 01 — About Me

Engineer, researcher, and silicon problem hunter.

Hello! I'm Md Kamrul Islam, a Senior Design Verification Engineer at ULKASEMI Pvt. Limited based in Dhaka, Bangladesh. I work where RTL intent meets real sign-off pressure: UVM testbenches, gate-level simulation, coverage closure, waveform debug, and automation. Humanity invented invisible bugs inside chips and then hired people like me to hunt them. Naturally.

My work combines verification planning, reusable UVM methodology, GLS debug, client communication, and mentoring junior engineers. I'm especially interested in VLSI reliability, ASIC design and verification, secure SoC architecture, and automation that saves engineers from doing the same painful task twice.

Current Role
Senior Engineer,
Design Verification
ULKASEMI Pvt. Limited · Dhaka, Bangladesh
Based In
Dhaka, Bangladesh
Focus
UVM · GLS · DDR PHY
Style
Metric-driven debug
Research
PV · ML · VLSI
// 02 — Education

Academic Background

BSc in Electrical and Electronic Engineering
BRAC University
BRAC University · Dhaka, Bangladesh
Period: Spring 2016 – Fall 2020 CGPA: 3.51 / 4.00 Credits: 164.5 Major: Electronics & Power Minor: Computer Science
Undergraduate Thesis
Islam, M. K., Shawon, M. M. H., Akter, S., & Ahmed, S. (2020). Outdoor performance analysis and prediction of photovoltaic modules using machine learning algorithm. BRAC University.  ↗ Download PDF
// 03 — Research

Research & Publications

Research interests at the intersection of hardware reliability, intelligent systems, and secure SoC architecture.

Variation-aware low-power VLSI design AI / neuromorphic accelerators Secure & reliable SoC architectures ASIC design and verification
2020
Short-term performance investigation of solar PV module: A machine learning based approach
Ahmed, S., Islam, M. K., Islam, M., & Rahman, M. M.
IEEER10-HTC 2020DOI ↗PDF ↗
2020
Forecasting PV panel output using Prophet time series machine learning model
Hasan Shawon, M. M., Akter, S., Islam, M. K., Ahmed, S., & Rahman, M. M.
IEEETENCON 2020DOI ↗PDF ↗
2020
Degradation of PV module performance due to dust accumulation on high-rise buildings
Akter, S., Shawon, M. M. H., Islam, M. K., Ahmed, S., & Rahman, M. M.
IEEEWIECON-ECE 2020DOI ↗PDF ↗
// 04 — Projects

Verification projects with measurable outcomes.

NOV 2024 — PRESENTCLIENT · CURRENT
GLS-based Verification of DDR PHY IPs

Gate-level sign-off readiness of DDR PHY IP through multi-corner GLS regressions, X-propagation debug, UVM updates, and power-analysis support.

  • Resolved 30+ tape-out critical functional issues
  • Reduced GLS debug cycles by ~30% via automation
  • Led a team of 3 engineers to hit milestones
SVUVMVCSVerdiPythonBashPerforce
AUG 2024 — NOV 2024GLS READINESS
Testbench GLS Readiness & Refactoring

Refactored RTL-provided linear testbench, automated GLS execution, and debugged X-propagation failures to stabilise regressions.

  • Improved GLS readiness and regression stability
  • Enabled repeatable GLS execution with lower manual effort
SVCadence IUSSimVisionBash
NOV 2023 — MAY 2024INTERNAL IP
Real-Time Clock (RTC) IP Verification

End-to-end verification sign-off of RTC IP with reusable UVM methodology, RAL model, coverage model, assertions, and waiver tracking.

  • Achieved ~98% functional and code coverage
  • Caught 25+ functional bugs
  • Reduced verification time by ~30% using Bash automation
SVUVMXceliumRALGit
SEP 2022 — JUL 2023CLIENT PROJECT
USB Power Delivery Controller Verification

Verified USB-PD controller subsystems across RTL and GLS through constrained-random tests, global assertions, coverage models, and regression triage.

  • Found 25+ pre-silicon functional bugs
  • Contributed to first-silicon success
SVUVMvManagerSVA
MAR 2022 — AUG 2022TRAINEE VERIFICATION
Wishbone-I2C, APB-SPI & AMBA APB/AHB Verification

Built multi-agent UVM testbench for Wishbone-I2C and APB-SPI, and single-agent for APB/AHB; authored test/coverage plans and automation scripts.

  • Achieved >90% functional coverage
  • Cut test cycle time ~30% with Bash/Python automation
SVUVMXceliumBash
AUG 2019 — JUN 2020RESEARCH THESIS
PV Module Performance Prediction using ML

Built a rooftop PV/weather data acquisition setup and ANN/MLP workflow to analyse clean vs. dusty PV module behaviour under real environmental conditions.

  • Published 3 IEEE conference papers
  • Found temperature as most correlated parameter with PV output
Raspberry PiArduinoPythonANN
// 05 — Experience

Professional Journey

Current
Senior Engineer, Design Verification
ULKASEMI Pvt. Limited
Jan 2025 — Present
  • Lead and mentor engineers on client projects — recruitment, training, task allocation, weekly client meetings.
  • Own DV strategy, verification plan, UVM testbench architecture, functional coverage, assertions, and sign-off.
  • Run GLS regressions; debug complex timing/X-propagation issues; drive root-cause fixes toward tape-out.
Engineer, Design Verification
ULKASEMI Pvt. Limited
Jan 2024 — Dec 2024
  • Executed DV tasks independently on client projects; weekly client status meetings.
  • Built and maintained UVM tests, sequences, agents/environments, constrained-random tests for corner scenarios.
  • Drove coverage closure, regressions, failure debug with design/architecture teams.
Assistant Engineer, Design Verification
ULKASEMI Pvt. Limited
May 2022 — Dec 2023
  • Implemented testcases, UVM components, assertions, and coverage items under senior guidance.
  • Executed regressions, analyzed waveform failures, reproduced issues, and updated bug reports.
Trainee Engineer, Design Verification
ULKASEMI Pvt. Limited
Feb 2022 — May 2022
  • Completed structured training on SystemVerilog/UVM and simulation compile/run/debug flow.
  • Wrote smoke tests, sanity tests, basic sequences, and utilities following daily milestones.
Software Engineer Intern
SpaGreen Creative
Oct 2021 — Feb 2022
  • Developed cross-platform mobile applications using Flutter for Android and iOS.
  • Implemented UI/UX designs into functional app screens, managed state, and integrated REST APIs.
  • Collaborated in an agile team environment from initial design through deployment on app stores.
Student Tutor — EEE301
BRAC University, Department of EEE
Jun 2021 — Sep 2021
  • Conducted topic sessions based on students' needs; assisted faculty with assessments.
  • Helped weaker students overcome difficulties in specific topics.
// 06 — Skills

Technical Expertise

EDA / Simulation & Debug
Synopsys VCSSynopsys VerdiCadence XceliumSimVisionvManagerICCR / IMCModelSim
Verification & Sign-off
Functional VerificationGate-Level SimulationSystemVerilog AssertionsConstrained-RandomCoverage-DrivenRegression
HDLs & Methodologies
SystemVerilogVerilogUVMRAL ModelingTLM
Protocols / IP Exposure
DDR-DRAM / DDR PHYDFIUSB PD ControllerRTCAMBA APB/AHBI2C / SPIPCIe Basics
Scripting & Automation
PythonBashPerlTCLMakefileC / C++
Version Control & Tracking
Git / GitHubPerforceDesignSyncJIRA
// 07 — Achievements & Certifications

Training & Certifications

Gate-Level Simulation Training — VLSIGuru ↗Jul 2025
GLS fundamentals, testbench setup, SDF timing, and power-aware verification basics.
DDR DRAM, DDR PHY, DFI & GLS Training — Synopsys Inc.Dec 2024
Completed during GLS-based DDR PHY verification project for Synopsys Inc.
UVM DV Training — Wishbone-I2C, APB-SPI & AMBA APB/AHBAug 2022
Built multi-agent UVM testbench; achieved >90% functional coverage; cut cycle time ~30% via Bash/Python.
Excel Skills for Business: Essentials — Macquarie University / Coursera ↗Mar 2021
Programming for Everybody (Python) — University of Michigan / Coursera ↗Mar 2020
Python Data Structures — University of Michigan / Coursera ↗Mar 2020
// 08 — Contact

Get in Touch

Open to collaborations, opportunities, and conversations about chip design verification, UVM methodology, GLS, and semiconductor engineering.

Email
md.kamrul.islam20feb@gmail.com
Phone
+880 1836 232 647
Location
Dhaka, Bangladesh
LinkedIn
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Google Scholar
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ResearchGate
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