Turning Complex IP into Verified Silicon

Design Verification Engineer with almost 4 years of hands-on experience verifying complex IP across RTL and gate-level domains. Delivered end-to-end verification for DDR, USB PD Controller, and RTC IPs, identifying 30+ silicon-critical bugs and achieving >95% coverage closure. Proficient in Synopsys VCS, Verdi, Cadence Xcelium, vManager and ModelSim, with Bash/Python scripting that cuts debug cycles by 30–40%.

Found 30+ silicon-critical Bugs

>95% Functional Coverage

20–30% faster GLS debug

Delivered 3 Client projects

Mentored 6 Junior Engineers

Trained 36 Trainees

Education

Bachelor of Science in Electrical and Electronic Engineering

Spring 2016 - Fall 2020

Institution: BRAC University, Dhaka, Bangladesh

CGPA: 3.51/4.00 | Credits Earned: 164.5

Major Concentration: Electronics and Power

Minor Concentration: Computer Science

Thesis: Islam, M. K., Shawon, M. M. H., Akter, S., & Ahmed, S. (2020). Outdoor performance analysis and prediction of photovoltaic modules using machine learning algorithm. [Undergraduate thesis, Brac University]. BracU Institutional Repository. Download

Research Interests

Variation-aware Low-power VLSI Design AI/Neuromorphic Accelerators Secure and Reliable SoC Architectures ASIC Design and Verification

Google Scholar Research Gate

Conference Publications

Ahmed, S., Islam, M. K., Islam, M., & Rahman, M. M. (2020). Short-term performance investigation of solar PV module: A machine learning based approach. In 2020 IEEE 8th R10 Humanitarian Technology Conference (R10-HTC) (pp. 1–6). IEEE. Download
Hasan Shawon, M. M., Akter, S., Islam, M. K., Ahmed, S., & Rahman, M. M. (2020). Forecasting PV panel output using Prophet time series machine learning model. In 2020 IEEE Region 10 Conference (TENCON) (pp. 1141–1144). IEEE. Download
Akter, S., Shawon, M. M. H., Islam, M. K., Ahmed, S., & Rahman, M. M. (2020). Degradation of PV module performance due to dust accumulation on high-rise buildings. In 2020 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE) (pp. 239–242). IEEE. Download

Research & Project Experiences

GLS-based Verification of DDR PHY IPs • Nov'2024 - Present

Project Type: Ulkasemi's Client Project
Target: Ensure gate-level sign-off readiness of DDR PHY IP through multi-corner GLS (SDF and 0-delay) and Gate-Level regression closure for tape-out milestones.
Responsibilities:

Leading a team of 1 engineer and 2 assistant engineers to achieve set milestones to meet the project deadline
Running multi-corner (SDF MAX/MIN and 0-Delay) GLS regressions
Debugging timing, X-propagation, and functional failures
Updating/enhancing UVM testbench and verification environment to match evolving IP
Generating optimized VCD deliverables for Design Implementation team for Power analysis
Writing automation scripts to streamline runs/debug
Maintaining the changes made in the codebase using version control tool Perforce
Reporting identified bugs and their fixes on JIRA for tracking the verification flow

Outcomes:

Identified/resolved 30+ tape-out critical functional issues across multiple products of DDR PHY and reduced GLS debug cycles by ~30% through automation scripts
Distributed tasks among the 3 assistant engineers and conducted weekly meeting with client to speed up the whole process and to meet the deadline

Tools Usage: SystemVerilog, UVM, Synopsys VCS, Synopsys Verdi, Perl, Python, Bash, Makefile, Perforce, JIRA

Testbench GLS Readiness & Refactoring • Aug'2024 — Nov'2024

Project Type: Ulkasemi's Client Project
Target: Make RTL-provided linear testbench GLS-ready and establish a reliable, automated GLS regression flow.
Responsibilities:

Reviewed and refactored linear testbench for GLS compatibility
Automated GLS execution and run orchestration
Debugged multiple X-propagation and compilation issues to improve and stabilize pass rate

Outcomes:

Improved GLS readiness and regression stability
Reduced manual run effort and enabled repeatable GLS execution

Tools Usage: SystemVerilog, Cadence IUS, Cadence SimVision, Bash

Real-Time Clock (RTC) IP Verification • Nov'2023 - May'2024

Project Type: Ulkasemi's Internal Project
Target: Own end-to-end verification sign-off of RTC IP with strong functional/code coverage and reusable methodology.
Responsibilities:

Developed verification plan for functional test, assertions and coverage implementation
Implemented testcases, UVM RAL model, coverage model, and SystemVerilog assertions
Developed reusable UVMF-style environment to speed up register access and test development
Reported functional bugs and their fixes on GitHub to track the verification flow.
Maintained the changes made in the codebase using version control tool Git
Tracked waivers and drove closure with proper documentation

Outcomes:

Achieved ~98% functional and code coverage (with tracked waivers)
Caught 25+ functional bugs and confirmed fixes with RTL designer
Reduced verification time by ~30% by automating test runs using Bash

Tools Usage: SystemVerilog, UVM, Cadence Xcelium, SimVision, ICCR, IMC, Bash, Git, GitHub

USB Power Delivery Controller Sub-system Verification • Sep'2023 - Jul'2023

Project Type: Ulkasemi's Client Project
Target: Verify USB-PD controller sub-systems across RTL + Gate-Level Simulations and support first-silicon success through developing Constrained Random Tests, Global checker (assertions), Functional coverage model.
Responsibilities:

Developed testplan for functional behavior of different block across the sub-system
Developed 80+ constrained random testcases for state machines, and timing paths
Implemented global checkers using SystemVerilog Assertions
Ran and managed regressions though Cadence vManager
Executed multi-corner (SDF Max, Min and Zero Delay) Gate-Level Simulation regressions
Triaged Gate-Level functional issues, documented and reported their fixes
Maintained the changes made in the codebase using version control tool DesignSync

Outcomes:

Found 25+ pre-silicon functional bugs
Contributed to first-silicon success
Improved regression triage/sign-off efficiency through structured failure signature analysis

Tools Usage: SystemVerilog, UVM, Cadence Xcelium, Cadence SimVision, vManager, Bash, Perl, DesignSync

Outdoor Performance Analysis and Prediction of Photovoltaic Modules Using Machine Learning Algorithm • Aug'2019 - Jun'2020

Project Type: Undergraduate Thesis Project
Target: PV module performance under real weather conditions, quantify dust impact (clean vs. dusty), and predict PV current/energy using ANN/MLP models.
Responsibilities:

Designed a rooftop setup with two mono-Si PV modules (clean vs. dusty)
Built a Raspberry Pi–based weather station to log PV module output (Short-circuit current) and environmental data (temp, humidity, wind, pressure)
Derived solar irradiance and prepared datasets (CSV) for modeling.
Wrote Python scripts to collect, clean, and prepare data for training machine learning models.
Developed an ANN model to predict the output of the mono-Si PV modules based on the trained dataset.

Outcomes:

Found temperature as the most correlated parameter with PV module output
Achieved MLP prediction performance Short-circuit Current: clean panel avg. % diff -1.92% to 2.21% (RMSE 23.96–37.96) and dusty panel avg. % diff -7.32% to 13.35% (RMSE 22.11–61.22); Energy: clean -1.87% to 7.9%, dusty -4.21% to 8.67%
Showed temperature-only inputs produced ~0.76% average difference in cumulative light energy vs. using all weather parameters (in the studied comparison).

Tools Usage: Raspberry Pi 3B+, Arduino UNO, INA219, DS18B20, DHT11, BMP180, anemometer, PuTTY, TightVNC, Python, ANN

Professional Experiences

Senior Engineer, Design Verification, Digital • ULKASEMI Pvt. Limited • Jan'2025 - Present

Responsibilities:

Lead and mentor a team of engineers/assistant engineers on client projects, including recruitment, training, task allocation, technical guidance, work reviews, and weekly client status/issue meetings.
Own and drive the verification plan, DV strategy, and sign-off for blocks/subsystems, collaborating with design/architecture and cross-functional teams to clarify specifications and close issues.
Architect and maintain UVM testbenches, implementing functional coverage and assertions and achieving coverage closure with justified waivers.
Run and manage regressions and GLS activities, debugging complex protocol/timing/corner issues, supporting integration, low-power/reset/clocking scenarios, and driving root-cause fixes with design towards sign-off.

Engineer, Design Verification, Digital • ULKASEMI Pvt. Limited • Jan'2024 - Dec'2024

Responsibilities:

Executed DV tasks independently on client projects, supporting the team lead and participating in weekly client meetings to report status and discuss issues.
Built and maintained UVM tests, sequences, and extended agents/environments; developed directed and constrained-random tests for corner/error scenarios; maintained scoreboards, checkers, monitors, and reference models.
Drove coverage closure, ran regressions, debugged failures with design/architecture teams, and improved automation and overall testbench stability.

Assistant Engineer, Design Verification, Digital • ULKASEMI Pvt. Limited • May'2022 - Dec'2023

Responsibilities:

Assisted team lead/senior engineers in verification tasks by implementing testcases/sequences and small UVM testbench components, adding assertions and coverage items per DV guidelines and code style.
Executed regressions, analyzed failures via waveforms/debug, reproduced and narrowed down issues, updated test plans/logs/bug reports, and collaborated with other teams when needed.

Trainee Engineer, Design Verification, Digital • ULKASEMI Pvt. Limited • Feb'2022 - May'2022

Responsibilities:

Completed structured training on SystemVerilog (SV)/UVM, simulation flow (compile/run/debug), and the project environment; wrote and executed smoke/sanity tests, basic sequences, and small utilities.
Followed training plans and completed daily verification milestones for assigned practice projects.

Student Tutor (EEE301), Department of EEE • BRAC University • Jun'2021 - Sep'2021

Responsibilities:

Conducted short classes/sessions on specific topics based on students’ need.
Assisted course faculty with recording marks for Quizzes, Mid, Final, Assignments.
Helped weaker students overcome difficulties with particular topics.

Technical Skills

EDA / Simulation & Debug

Synopsys VCS, Synopsys Verdi
Cadence Xcelium, Cadence SimVision
Cadence vManager, Cadence ICCR, Cadence IMC
Intel ModelSim

Verification & Sign-off

Functional Verification
Gate-Level Simulation
SystemVerilog Assertions (SVA)
Constrained-Randomization
Metric-/Coverage-Driven Verification
Regression

HDLs & Methodologies

SystemVerilog
Verilog
UVM (Universal Verification Methodology)
UVM Register Abstraction Layer (RAL) Modeling
Transaction Level Modeling (TLM)

Programming & OOP

C/C++
Python

Protocols / IP Exposure

DDR-DRAM, DDR PHY, DFI
USB PD Controller
RTC
AMBA (APB, AHB)
I2C, SPI
PCIe (Basics Knowledge)

Scripting & Automation

Python
Bash
Perl
TCL

Version Control / Tracking

Git, GitHub
Perforce
DesignSync
JIRA

Training & Certifications

Gate-Level Simulation Training by VLSIGuru — GLS fundamentals, testbench setup, SDF timing, and power-aware verification basics. (Jul'2025)
Completed training modules on DDR DRAM, DDR PHY, DFI, and GLS during GLS-based DDR PHY verification project for Synopsys Inc. (Dec'2024)
Completed UVM DV Training on Wishbone-I2C, APB-SPI & AMBA APB/AHB IP Verification - Built a multi-agent UVM testbench for Wishbone-I2C, APB-SPI and single-agent for APB/AHB; authored test/coverage plans; achieved >90% functional coverage, and developed Bash/Python script automation to cut test cycle time ~30%. (Aug'2022)
Completed “ Excel Skills for Business: Essentials ” course offered by Macquarie University on Coursera. (Mar'2021)
Completed “ Programming for Everybody (Getting Started with Python) ” course offered by University of Michigan on Coursera. (Mar'2020)
Completed “ Python Data Structure ” course offered by University of Michigan on Coursera. (Mar'2020)

Contact

Location: Dhaka, Bangladesh

Phone: +880 1836 232 647

Email: md.kamrul.islam20feb@gmail.com

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